ATMEGA169P-16MCHR【PDF 46/274 页】MCU AVR 16KB FLASH 16MHZ 64-VQFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3753

42页 43页 44页 45页 [46页]47页 48页 49页 50页

8018P–AVR–08/10

ATmega169P

6.4.1

SPH and SPL – Stack Pointer

6.5

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk

CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 6-2 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 6-2.

The Parallel Instruction Fetches and Instruction Executions

Figure 6-3 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Figure 6-3.

Single Cycle ALU Operation

Bit

151413121110

0x3E (0x5E)

–

SP10

SP9

SP8

SPH

0x3D (0x5D)

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

SPL

765

43210

Read/Write

R/W

Initial Value

000

00000

000

00000

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

clk

CPU

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式